Semiconductor memory device with 3d structure

ABSTRACT

A semiconductor memory device with a three-dimensional (3D) structure may include: a cell region arranged over a substrate, including a cell structure; a peripheral circuit region arranged between the substrate and the cell region; an upper wiring structure arranged over the cell region; main channel films and dummy channel films formed through the cell structure. The dummy channel films are suitable for electrically coupling the upper wiring structure.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a division of U.S. patent application Ser. No.16/716,929 filed on Dec. 17, 2019, which is a continuation of U.S.patent application Ser. No. 15/352,765 filed on Nov. 16, 2016, whichissued as U.S. Pat. No. 10,546,814 on Jan. 28, 2020, and claims thebenefits of priority of Korean Patent Application No. 10-2016-0098284filed on Aug. 2, 2016. The disclosure of each of the foregoingapplication is incorporated herein by reference in their entirety.

BACKGROUND 1. Field

Exemplary embodiments of the present invention relate to a semiconductordevice and, more particularly, to a semiconductor memory device with athree-dimensional (3D) structure.

2. Description of the Related Art

Due to the continuing advances of the electronic industriessemiconductor memory devices with improved performance and lower costare needed. To meet these requirements, 3D semiconductor memory devicesin which memory cells are arranged in a plurality of cell strings in athree-dimensional structure have been proposed. 3D semiconductor memorydevices provide substantial improvements in the integration density ofsemiconductor memory devices. Recently, a variety of techniques havebeen developed to improve the characteristics and integration density ofsuch a 3D semiconductor memory device. However, further improvements areneeded.

SUMMARY

The present invention is directed to an improved three-dimensionalsemiconductor memory device and a method for manufacturing such device.

In an embodiment, a semiconductor memory device with a three-dimensional(3D) structure may include: a cell region arranged over a substrate,including a cell structure; a peripheral circuit region arranged betweenthe substrate and the cell region; an upper wiring structure arrangedover the cell region; main channel films and dummy channel films formedthrough the cell structure, wherein the dummy channel films are suitablefor electrically coupling the upper wiring structure.

In an embodiment, a semiconductor memory device with a three-dimensional(3D) structure may include: a cell region arranged over a substrate,including a cell structure; a peripheral circuit region disposed betweenthe substrate and the cell region; main channel films formed through thecell structure; first and second dummy channel films electricallycoupled to the peripheral circuit region through the cell structure; anda fuse disposed over the cell region and coupled between the first andsecond dummy channel films.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features and advantages of the present inventionwill become apparent to those skilled in the relevant art by thefollowing detailed description with reference to the attached drawingsin which:

FIG. 1 is a cross-sectional view of a semiconductor memory device with athree-dimensional (3D) structure according to an embodiment of thepresent invention.

FIG. 2 is a plan view of dummy channel films, dummy bit line contactsand an upper wiring structure, which are illustrated in FIG. 1 .

FIG. 3 is a cross-sectional view of a semiconductor memory device with athree-dimensional (3D) structure according to an embodiment of thepresent invention.

FIG. 4 is a plan view of dummy channel films, dummy bit line contactsand a first upper wiring layer, which are illustrated in FIG. 3 .

FIG. 5 is a cross-sectional view of a semiconductor memory device with athree-dimensional (3D) structure according to an embodiment of thepresent invention.

FIG. 6 is a plan view of dummy channel films, dummy bit line contacts, afirst upper wiring layer, first upper wiring contacts and a second upperwiring layer, which are illustrated in FIG. 5 .

FIG. 7 is a cross-sectional view of a semiconductor memory device with athree-dimensional (3D) structure according to an embodiment of thepresent invention.

FIG. 8 is a cross-sectional view of a semiconductor memory device with athree-dimensional (3D) structure according to an embodiment of thepresent invention.

FIG. 9 is a cross-sectional view of a semiconductor memory device with athree-dimensional (3D) structure according to an embodiment of thepresent invention.

FIG. 10 is a simplified block diagram schematically illustrating amemory system including a semiconductor memory device with athree-dimensional (3D) structure, according to an embodiment of theinvention.

FIG. 11 is a simplified block diagram schematically illustrating acomputing system including a semiconductor memory device with athree-dimensional (3D) structure, according to an embodiment of theinvention.

DETAILED DESCRIPTION

Hereafter, various embodiments will be described below in more detailwith reference to the accompanying drawings, such that the presentinvention can be practiced by those skilled in the art to which thepresent invention pertains. The drawings are not necessarily illustratedat a constant ratio, and at least a part of the structures illustratedin the drawings may be exaggerated in order to clarify thecharacteristics of embodiments. The drawings or detailed descriptions ofa multilayer structure may not reflect all layers existing in a specificmultilayer structure. For example, one or more additional layers mayexist between two layers. For example, when a first layer is beingreferred to as being formed on a second layer or substrate in amultilayer structure of the drawings or detailed description, it may notonly indicate that the first layer can be directly formed on the secondlayer or the substrate, but also indicate that one or more other layersexist between the first and second layers or between the first layer andthe substrate.

When different embodiments are described, any repetitive descriptions ofthe same components will be omitted, and the same components are denotedby like reference numerals.

Spatially relative terms, such as “under,” “below,” “lower,” “above,”“upper” and the like, may be used herein for ease of description todescribe one element or feature's relationship to another element(s) orfeature(s) as illustrated in the figures. It will be understood that thespatially relative terms are intended to encompass differentorientations of the device in manufacturing, use or operation inaddition to the orientation depicted in the figures. For example, if thedevice in the figures is turned over, elements described as “below” or“under” other elements or features would then be “above” the otherelements or features. The device may be otherwise oriented (rotated 90degrees or at other orientations) and the spatially relative descriptorsused herein interpreted accordingly.

In the following description, numerous specific details are set forth inorder to provide a thorough understanding of the present invention. Thepresent invention may be practiced without some or all of these specificdetails. In other instances, well-known process structures and/orprocesses have not been described in detail in order not tounnecessarily obscure the present invention.

It is also noted, that in some instances, as would be apparent to thoseskilled in the relevant art, an element (also referred to as a feature)described in connection with one embodiment may be used singly or incombination with other elements of another embodiment, unlessspecifically indicated otherwise.

Referring to FIGS. 1 and 2 , a cell region CELL is formed over asubstrate 10, and a peripheral circuit region PERI is formed between thecell region CELL and the substrate 10.

The substrate 10 may include one of a silicon (Si) substrate, agermanium (Ge) substrate, a silicon-germanium (SiGe) substrate, aSilicon-On-Insulator (SOI) substrate or a Silicon-Germanium-Insulator(SGOI) substrate. An isolation layer 11 may be formed at an upper regionof substrate 10 partially covering the substrate and defining an activeregion 10A.

The cell region CELL may include a plurality of memory cells arrangedtherein. The peripheral circuit region PERI may include one or moreperipheral circuits arranged therein.

The peripheral circuit region PERI may vertically overlap the cellregion CELL at the bottom of the cell region CELL. Since the peripheralcircuit region PERI overlaps the cell region CELL, the size of thesemiconductor memory device is reduced because utilization of the areaof the substrate 10 is increased.

The peripheral circuits arranged in the peripheral circuit region PERImay include a data processing circuit capable of processing datainputted to or outputted from the memory cells arranged in the cellregion CELL. The peripheral circuits may include a test logic circuitcapable of testing whether the semiconductor memory device is normallyoperated. For example, the data processing circuit may include a rowdecoder, a page buffer, an input/output buffer, a control logic, avoltage generator and the like. The test logic circuit may be used totest whether the semiconductor memory device is normally operated, atthe final step of the process for fabricating the semiconductor memorydevice.

In the illustrated embodiment, the peripheral circuit region PERI mayinclude peripheral circuit elements PRT1 and PTR2 constituting theperipheral circuits and a lower wiring structure LML electricallycoupled to the peripheral circuit elements PTR1 and PRT2. The peripheralcircuit elements PTR1 and PTR2 may include peripheral transistors. Eachof the transistors may include a gate PG and impurity regions PS and PD.The gate PG may be formed over the substrate 10. The impurity regions PSand PD may be formed in an active region 10A defined by the isolationlayer 11 at both sides of the gate PG, and serve as a source and drain,respectively.

Over the substrate 10, interlayer insulation films (or layers) 21, 22and 23 are formed to cover the peripheral circuit elements PTR1 and PTR2and the lower wiring structure LWL. The interlayer insulation films 21,22, and 23 may be sequentially stacked. The first to third interlayerinsulation films 21, 22, and 23 may include silicon oxide, siliconoxynitride and the like.

The lower wiring structure LML may be formed in the first to thirdinterlayer insulation films 21, 22, and 23. The lower wiring structureLML may include a first lower wiring contact 31, a first lower wiringlayer 32, a second lower wiring contact 33 and a second lower wiringlayer 34. The first lower wiring layer 32 may be formed on the firstinterlayer insulation film 21, and may be electrically coupled to theperipheral circuit elements PTR1 and PTR2 through the first lower wiringcontact 31. More specifically, the first lower wiring contact 31 may bean elongated element which extends substantially vertically through thefirst interlayer insulation film 21 to couple the first lower wiringlayer 31 with the peripheral circuit elements PTR1 and PTR2. The secondlower wiring layer 34 may be formed on the second interlayer insulationfilm 22, and may be electrically coupled to the first lower wiring layer32 through the second lower wiring contact 33. The second lower wiringcontact 33 may be an elongated element extending vertically within thesecond interlayer insulation film to connect the second lower wiringlayer 34 with the first lower wiring layer 31.

The peripheral circuit elements PTR1 and PTR2 may include high-voltagetransistors for transmitting a high voltage. Thus, when thesemiconductor memory device is operated, the peripheral circuit elementsPTR1 and PTR2 may generate a large amount of heat. Since the lowerwiring structure LML is disposed close to the peripheral circuitelements PTR1 and PTR2, the lower wiring structure LML may be formed ofa metal which has a high fusing point to withstand the heat generatedfrom the peripheral circuit elements PTR1 and PTR2. For example, thelower wiring structure LML may be made of a metal such as tungsten,molybdenum, titanium, cobalt, tantalum or nickel.

In the present embodiment, the lower wiring structure LML has astructure in which two lower wiring layers 32 and 34 are coupled by twolower wiring contacts 31 and 33. However, depending on the layout of theperipheral circuit elements formed in the peripheral circuit region PERIand the type and arrangement of the peripheral circuit elements, thelower wiring structure LML may have a structure in which one or morelower wiring layers are coupled by one or more lower wiring contacts.

The cell region CELL may have a cell structure 40 formed therein. Thecell structure 40 may include a plurality of cell gate conductive films41 and a plurality of insulation films 42. The plurality of cell gateconductive films 41 may be spaced apart from each other at a regularinterval in the vertical direction, and the plurality of insulationfilms 42 formed between the respective gate insulation films 42 forinsulating the respective cell gate conductive films 41 from each other.

The cell gate conductive films 41 may include a metal such as tungsten,nickel, cobalt or tantalum, impurity-doped polysilicon, a metal silicidesuch as tungsten silicide, nickel silicide, cobalt silicide or tantalumsilicide, or combinations thereof. The insulation films 42 may includesilicon oxide, silicon nitride, silicon oxynitride and the like.

Among the cell gate conductive films 41, one or more layers from thelowermost layer may be used as a select line of a source selecttransistor, one or more layers from the uppermost layer may be used as aselect line of a drain select transistor. The conductive films betweenthe select lines may be used as word lines, with each word line beingoperatively coupled to a plurality of memory cells.

The cell region CELL may include main channel films CH formed throughthe cell structure 40 in a direction perpendicular to the top surface ofthe substrate 10. The main channel films CH may include impurity-dopedpolysilicon or undoped polysilicon.

The main channel films CH may be buried in through-holes formed in thecell structure 40 to completely fill the through-holes. In an embodiment(not shown) Although not illustrated, in an embodiment, each of the mainchannel films CH may be formed in a tube shape surrounding an insulationfilm which fills the central region of the corresponding through-hole,along the sidewall of the through-hole passing through the cellstructure 40. The main channel films CH may have a structure includingone of the burial-type structure and the tube-type structure.

The select transistors may be formed at the respective intersectionsbetween the select lines and the main channel films CH. The memory cellsmay be formed at the respective intersections between the word lines andthe main channel films CH. In such a structure, the select transistorsand the memory cells may be coupled in series by the main channel filmsCH, and constitute cell strings ST.

Between the main channel films CH and the cell structure 40, a gateinsulation film (not illustrated) may be formed to cover the outer wallsof the main channel films CH. The gate insulation film may include atunnel insulation film, a charge storing film and a blocking insulationfilm, which are sequentially stacked therein. The tunnel insulation filmmay include silicon oxide, hafnium oxide, aluminum oxide, zirconiumoxide, tantalum oxide and the like. The charge storing film may includesilicon nitride, boron nitride, silicon boron nitride or impurity-dopedpolysilicon. The blocking insulation film may include a single-layer ormultilayer structure of silicon oxide, silicon nitride, hafnium oxide,aluminum oxide, zirconium oxide and tantalum oxide.

Between the cell region CELL and the peripheral circuit region PERI, asemiconductor pattern 50 may be formed. The semiconductor pattern 50 mayoverlap the cell structure 40 except for an area of the cell structure40 that includes dummy channel films DCH. More specifically, thesemiconductor pattern 50 may define an opening 51 below an area of thecell structure 40 that includes the dummy channel films DCH.

The semiconductor pattern 50 may serve as a common source region whichis electrically coupled to the main channel films CH and supplies acommon source voltage to the cell strings ST. The semiconductor pattern50 may be formed by doping an impurity-doped semiconductor or undopedintrinsic semiconductor with p-type or n-type impurities, the impurityincluding a group III element, group IV element and/or group V element.The semiconductor pattern 50 may include a pipe gate electrode. Such anembodiment will be clarified through the following descriptions withreference to FIG. 9 .

Over the third interlayer insulation film 23, interlayer insulationfilms 24 to 26 may be formed to cover the semiconductor pattern 50 andthe cell structure 40. The interlayer insulation films 24 to 26 mayinclude fourth to sixth interlayer insulation films 24 to 26 which aresequentially stacked. The fourth to sixth interlayer insulation films 24to 26 may include silicon oxide and silicon oxynitride.

An upper wiring structure UML may include a first upper wiring layer 71,a first upper wiring contact 72, a second upper wiring layer 73, asecond upper wiring contact 74 and an external connection pad 75. In theembodiment of FIG. 1 , one first upper wiring contact 72, one secondupper wiring layer 73, one second upper wiring contact 74 and oneexternal connection pad 75 are formed. However, two or more first upperwiring contacts 72, two or more second upper wiring layers 73, two ormore second upper wiring contacts 74 and two or more external connectionpads 75 may be formed.

The first upper wiring layer 71 may be formed on the fourth interlayerinsulation film 24, and include bit lines BL, common source lines CSLand dummy bit lines DBL.

The bit lines BL may be electrically coupled to the main channel filmsCH through bit line contacts BLC formed through the fourth interlayerinsulation film 24. The common source line CSL may serve to transmit acommon source voltage to the semiconductor pattern 50 used as the commonsource region. Although not illustrated, in an embodiment, the commonsource line CSL may be electrically coupled to the semiconductor pattern50 through a contact plug formed through the fourth interlayerinsulation film 24.

In order to prevent a reduction of the breakdown voltage (BV)characteristic due to potential differences between the common sourcelines CSL and the bit lines BL, the dummy bit lines DBL may be arrangedbetween the common source lines CSL and the bit lines BL.

The second upper wiring layer 73 may be formed on the fifth interlayerinsulation film 25, and may be electrically coupled to the dummy bitlines DBL through the first upper wiring contact 72. The first upperwiring contact 72 may be an elongated element extending substantiallyvertically inside the fifth interlayer insulation layer 25 to connectthe second upper wiring layer 73 with the first upper wiring layer 71.

The external connection pad 75 may be formed on the sixth interlayerinsulation film 26, and may be electrically coupled to the second upperwiring layer 73 through the second upper wiring contact 74. The secondupper wiring contact 74 may be an elongated element extending verticallyinside the sixth interlayer insulation film 26 to electrically connectthe external connection pad 75 with the second upper wiring layer 73.The external connection pad 75 may serve as an external contact point ofthe semiconductor memory device, which is used for electrical connectionwith an external device, and overlap the cell structure 40. Apassivation film 27 exposing the external connection pad 75 may beformed on the sixth interlayer insulation film 26.

The upper wiring structure UML may be formed of a conductive materialhaving a low surface resistance. The conductive material forming theupper wiring structure UML may have lower surface resistance than aconductive material forming the lower wiring structure LML. For example,the upper wiring structure UML may be formed of a metal such as aluminum(Al), copper (Cu), silver (Ag) or gold (Au).

In the present embodiment, the upper wiring structure UML has two upperwiring layers 71 and 73. However, the upper wiring structure UML mayinclude one, three or more upper wiring layers.

Under the dummy bit line DBL, dummy channel films DCH may be formedthrough the cell structure 40 in a direction perpendicular to the topsurface of the substrate 10. Each of the dummy channel films DCH mayoverlap any one of the dummy bit lines DBL.

The dummy channel films DCH may be formed at the same time as the mainchannel films CH are formed. The dummy channel films DCH may havesubstantially the same structure as the main channel films CH.

The dummy channel films DCH may be buried in through-holes formed in thecell structure 40 to fill the through-holes. Although not illustrated,in an embodiment, each of the dummy channel films DCH may be formed in atube shape surrounding an insulation film which fills the central regionof the corresponding through-hole, along the sidewall of thethrough-hole passing through the cell structure 40. The dummy channelfilms DCH may have a structure including one of the burial-typestructure and the tube-type structure.

Between the dummy channel films DCH and the cell structure 40, a gateinsulation film (not illustrated) may be interposed to cover the outerwalls of the dummy channel films DCH. The gate insulation film mayinclude a tunnel insulation film, a charge storing film and a blockinginsulation film, which are sequentially stacked. The tunnel insulationfilm may include silicon oxide, hafnium oxide, aluminum oxide, zirconiumoxide, tantalum oxide and the like. The charge storing film may includesilicon nitride, boron nitride, silicon boron nitride or impurity-dopedpolysilicon. The blocking insulation film may include a single-layer ormultilayer structure of silicon oxide, silicon nitride, hafnium oxide,aluminum oxide, zirconium oxide and tantalum oxide.

The dummy bit lines DBL may be electrically coupled to the dummy channelfilms DCH through dummy bit line contacts DBLC formed through the fourthinterlayer insulation film 24.

The semiconductor pattern 50 may include an opening 51 overlapping thedummy channel films DCH. The opening 51 may be filled with an insulatinggap-fill layer 52. The insulating gap-fill layer 52 may include siliconoxide.

Between the dummy channel films DCH and the lower wiring structure LML,vertical contacts 60 may be formed to electrically couple the dummychannel films DCH and the lower wiring structure LML through theinsulating gap-fill layer 52 and the third interlayer insulation film23. Each of the vertical contacts 60 may overlap any one of the dummychannel films DCH. More specifically, each vertical contact 60 may be anelongated element having a top surface that has substantially the samecross section as the bottom surface of the corresponding dummy channelfilm DCH. Each vertical contact 60 may be tapered having a bottomsurface with a cross-sectional area that is smaller than thecross-sectional area of the top surface of the vertical contact 60 thatabuts the bottom surface of the corresponding dummy channel film DCH.

The vertical contacts 60 may be formed of a metal such as tungsten,molybdenum, titanium, cobalt, tantalum or nickel, a metal silicide suchas tungsten silicide, titanium silicide, nickel silicide, cobaltsilicide or tantalum silicide, or combinations thereof.

The external connection pad 75 may be electrically coupled to theperipheral circuit region PERI through the upper wiring structure UML,the dummy bit line contacts DBLC, the dummy channel films DCH and thevertical contact 60.

For example, the external connection pad 75 may be electrically coupledto the data processing circuit formed in the peripheral circuit regionPERI. In this case, the external connection pad 75 may correspond to anexternal input/output (I/O) pad serving as an external interface betweenthe semiconductor memory device and an external device. The externalconnection pad 75 may be electrically coupled to the test logic circuitformed in the peripheral circuit region PERI. In this case, the externalconnection pad 75 may serve as a test pad configured to perform a testof the semiconductor memory device.

The external connection pad 75 may be electrically coupled to theperipheral circuit region PERI through the dummy channel films DCHformed through the cell structure 40. Thus, a routing path whichelectrically couples the external connection pad 75 and the peripheralcircuit region PERI can be shortened to a smaller length than when therouting path is formed to bypass the cell structure 40.

When the routing path is lengthened, the capacitance and resistance maybe increased. Then, while the influence of noise increases, a signal maybe distorted during a signal transmission process, thereby reducingsignal integrity. According to the present embodiment, since the routingpath between the external connection pad 75 and the peripheral circuitregion PERI can be shortened, the signal integrity can be improved.

Furthermore, the external connection pad 75 and the peripheral circuitregion PERI are electrically coupled through the dummy channel films DCHoverlapped by the dummy bit lines DBL which are formed to prevent areduction of BV characteristic due to a potential difference between thecommon source lines CSL and the bit lines BL. Thus, the cell region CELLrequires no additional area for electrically coupling the externalconnection pad 75 and the peripheral circuit region PERI. Therefore, anadditional area for memory cells can be secured, thereby contributing toimproving the integration density of the semiconductor memory device.

FIGS. 1 and 2 illustrate that a plurality of external connection pads 75are electrically coupled to the peripheral circuit region PERI throughthe plurality of dummy channel films DCH and the plurality of verticalcontacts 60. However, one or more external connection pads may beelectrically coupled to the peripheral circuits through one or moredummy channel films and one or more vertical contacts.

FIGS. 1 and 2 illustrate that the plurality of main channel films CH areformed in the cell structure 40. However, the cell structure 40 mayinclude one or more main channel layers formed therein.

FIGS. 1 and 2 illustrate that the dummy channel films DCH are used toelectrically couple the peripheral circuit region PERI positioned underthe cell region CELL to the external connection pad 75 positioned abovethe cell region CELL. However, the dummy channel films DCH may be usedto electrically couple the peripheral circuit elements PTR1 and PTR2formed in the peripheral circuit region PERI. These embodiments will beclarified through the following descriptions with reference to FIGS. 3and 8 .

Referring to FIGS. 3 and 4 , a plurality of peripheral circuit elementsPTR1 and PTR2 may be formed in the peripheral circuit region PERI. Theperipheral circuit elements PTR1 and PTR2 may include a first peripheralcircuit element PTR1 and a second peripheral circuit element PTR2configured to receive a signal outputted from the first peripheralcircuit element PTR1.

Dummy channel films DCH1 and DCH2 may be formed under any one of thedummy bit lines DBL to pass through the cell structure in a directionperpendicular to the top surface of the substrate 10. The dummy channelfilms DCH1 and DCH2 may overlap any one of the dummy bit lines DBL.

The dummy channel films DCH1 and DCH2 may include a first dummy channelfilm DCH1 and a second dummy channel film DCH2. The first dummy channelfilm DCH1 may be electrically coupled to the first peripheral circuitelement PTR1 through a vertical contact 61 and a lower wiring structureLML1. The second dummy channel film DCH2 may be electrically coupled tothe second peripheral circuit element PTR2 through a vertical contact 62and a lower wiring structure LML2.

The first dummy channel film DCH1 may be electrically coupled to one endof any one of the dummy bit lines DBL through a first dummy bit linecontact DBLC1, and the second dummy channel film DCH2 may beelectrically coupled to the other end of the same dummy bit line DBLthrough a second dummy bit line contact DBLC2.

The first and second peripheral circuit elements PTR1 and PTR2 may bespaced apart at a considerable distance from each other along thedirection of the bit lines BL. Thus, in order to electrically couple thefirst and second peripheral circuit elements PTR1 and PTR2, a longrouting path extending in the direction of the bit line BL is required.

As described above, the conductive material forming the lower wiringstructure has a high resistance value. Therefore, when the first andsecond peripheral circuit elements PTR1 and PTR2 are connected throughthe lower wiring structure even though the first and second peripheralcircuit elements PTR1 and PTR2 are spaced a considerable distance fromeach other, the influence of noise may be increased by the highresistance value of the lower wiring structure. Thus, while a signal isdistorted during a signal transmission process, the integrity of thesignal provided to the second peripheral circuit element PTR2 may besignificantly degraded.

In the present embodiment, the length of each of the lower wiringstructures LML1 and LML2 is reduced whereas the dummy bit line of theupper wiring structure which is made of a material having a lowerresistance value than the lower wiring structures LML1 and LML2 isformed to a length required for connecting the first and second dummychannel films DCH1 and DCH2. More specifically, the lower wiringstructures LML1 and LML2 are each formed to a sufficient length connectthe first and second peripheral circuit elements PTR1 and PTR2 to thefirst and second dummy channel films DCH1 and DCH2, respectively,whereas the dummy bit line of the upper wiring structure which is madeof a material having a lower resistance value than the lower wiringstructures LML1 and LML2 is formed to a sufficient length that connectsthe first and second dummy channel films DCH1 and DCH2. Thus, theresistance of the routing path connecting the first and secondperipheral circuit elements PTR1 and PTR2 can be lowered, and thedistortion of a signal from the first peripheral circuit element PTR1while transmitted to the second peripheral circuit element PTR2 can beminimized, which makes it possible to improve the integrity of thesignal provided to the second peripheral circuit element PTR2.

Furthermore, since the lower wiring structures LML1 and LML2 and thedummy bit line DBL are connected through the dummy channel films DCH1and DCH2 formed through the cell structure 40, the routing path forelectrically coupling the lower wiring structures LML1 and LML2 and thedummy bit line DBL can be shortened to a smaller length than when therouting path is formed to bypass the cell structure 40. As a result,since the routing path between the first and second peripheral circuitelements PTR1 and PTR2 can be shortened, the distortion of a signal fromthe first peripheral circuit element PTR1 while transmitted to thesecond peripheral circuit element PTR2 can be minimized, which makes itpossible to improve the integrity of the signal provided to the secondperipheral circuit element PTR2.

FIGS. 3 and 4 illustrate that the first and second peripheral circuitelements PTR1 and PTR2 are spaced from each other along the direction ofthe bit lines BL, and the first and second peripheral circuit elementsPTR1 and PTR2 are electrically coupled through the dummy bit line DBL.

However, the first and second peripheral circuit elements PTR1 and PTR2may be spaced from each other along a direction perpendicular to the bitlines BL, and the first and second peripheral circuit elements PTR1 andPTR2 may be electrically coupled through the second upper wiring layer73 extended in the direction perpendicular to the bit lines BL. Such anembodiment will be clarified through the following descriptions withreference to FIGS. 5 and 6 .

Referring to FIGS. 5 and 6 , a plurality of peripheral circuit elementsPTR1 and PTR2 may be formed in the peripheral circuit region PERI. Theperipheral circuit elements PTR1 and PTR2 may include a first peripheralcircuit element PTR1 and a second peripheral circuit element PTR2configured to receive a signal outputted from the first peripheralcircuit element PTR1.

The first and second peripheral circuit elements PTR1 and PTR2 may bespaced apart at a considerable distance from each other in a directionperpendicular to the bit lines BL.

Dummy channel films DCH1 and DCH2 may be formed under dummy bit linesDBL1 and DBL2 to pass through the cell structure 40 in a directionperpendicular to the top surface of the substrate 10. The dummy channelfilms DCH1 and DCH2 may overlap the first and second dummy bit linesDBL1 and DBL2, respectively.

The dummy channel films DCH1 and DCH2 may include a first dummy channelfilm DCH1 and a second dummy channel film DCH2. The first dummy channelfilm DCH1 may be electrically coupled to the first peripheral circuitelement PTR1 through a vertical contact 61 and a lower wiring structureLML1. The second dummy channel film DCH2 may be electrically coupled tothe second peripheral circuit element PTR2 through a vertical contact 62and a lower wiring structure LML2.

The first dummy channel film DCH1 may be electrically coupled to thefirst dummy bit line DBL1 through a first dummy bit line contact DBLC1.The second dummy channel film DCH2 may be electrically coupled to thesecond dummy bit line DBL2 through a second dummy bit line contactDBLC2.

The second upper wiring layer 73 may be extended in a directionperpendicular to the bit lines BL and the first and second dummy bitlines DBL1 and DBL2. One end of the second upper wiring layer 73 may beelectrically coupled to the first dummy bit line DBL1 through a firstupper wiring contact 72A, and the other end may be electrically coupledto the second dummy bit line DBL2 through a second upper wiring contact72B.

Therefore, the first peripheral circuit element PTR1 may be electricallycoupled to the second peripheral circuit element PTR2 through the lowerwiring structure LML1, the vertical contact 61, the first dummy channelfilm DCH1, the first dummy bit line contact DBLC1, the first dummy bitline DBL1, the first upper wiring contact 72A, the second upper wiringlayer 73, the second upper wiring contact 72B, the second dummy bit lineDBL2, the second dummy bit line contact DBLC2, the second dummy channelfilm DCH2, the vertical contact 62 and the lower wiring structure LML2.

As described above, the conductive material forming the lower wiringstructures LML1 and LML2 has a high resistance value. Therefore, whenthe first and second peripheral circuit elements PTR1 and PTR2 arecoupled through the lower wiring structure even though the first andsecond peripheral circuit elements PTR1 and PTR2 are spaced aconsiderable distance from each other, the influence of noise may beincreased by the high resistance value of the lower wiring structure.Thus, while a signal is distorted during a signal transmission process,the integrity of the signal provided to the second peripheral circuitelement PTR2 may be degraded.

In the present embodiment, the lower wiring structures LML1 and LML2 areformed to such small lengths that connect the first and secondperipheral circuit elements PTR1 and PTR2 to the first and second dummychannel films DCH1 and DCH2, respectively. Further, the second upperwiring layer 73 made of a material having a lower resistance value thanthe lower wiring structures LML1 and LML2 is formed to a large length.Thus, since the resistance of a routing path connecting the first andsecond peripheral circuit elements PTR1 and PTR2 can be lowered, theintegrity of the signal provided to the second peripheral circuitelement PTR2 can be improved.

Furthermore, since the lower wiring structures LML1 and LML2 and thesecond upper wiring layer 73 are electrically coupled to each otherthrough the dummy channel films DCH1 and DCH2 formed through the cellstructure 40, the routing path for electrically coupling the lowerwiring structures LML1 and LML2 and the second upper wiring layer 73 canbe shortened to a smaller length than when the routing path is formed tobypass the cell structure 40. Thus, since the routing path between thefirst and second peripheral circuit elements PTR1 and PTR2 is shortened,the distortion of a signal from the first peripheral circuit elementPTR1 while transmitted to the second peripheral circuit element PTR2 canbe minimized, which makes it possible to improve the integrity of thesignal provided to the second peripheral circuit element PTR2.

In the embodiments of FIGS. 3 to 6 , the dummy bit line DBL or thesecond upper wiring layer 73 is used as a routing path for transmittinga signal. However, the dummy bit line DBL or the second upper wiringlayer 73 may be used as a fuse. Such an embodiment will be clarifiedthrough the following descriptions with reference to FIGS. 7 and 8 .

A semiconductor memory device may have an internal option which isdetermined according to the characteristic of a product to which thesemiconductor memory device is applied, and operate according to eachapplication program. A fuse may store such option information. Theoption information may be stored by electrically cutting the fuse.Furthermore, the fuse may further store repair information for a repairoperation of the semiconductor memory device.

Referring to FIG. 7 , a dummy bit line DBL may include a fuse which canbe electrically cut. The dummy bit line DBL may be electrically cut tostore option information or repair information. In FIG. 7 , CUTindicates a portion where the dummy bit line DBL is cut.

The peripheral circuit region PERI may include a fuse control circuitFSET configured to program a fuse made up of the dummy bit line DBL andverify a program state. The fuse control circuit FSET may provide ahigh-level program voltage to the dummy bit line DBL.

The fuse control circuit FSET may be electrically coupled to the dummybit line DBL through a lower wiring structure LML, a vertical contact60, a dummy channel film DCH and a dummy bit line contact DBLC, and cut(or program) the dummy bit line DBL by applying a program voltage to thedummy bit line DBL.

When a routing path between the fuse control circuit FSET and the dummybit line DBL is lengthened, the capacitance and resistance areincreased. Then, while the influence of noise increases, a signal may bedistorted during a signal transmission process, thereby causing anprogram error in which the dummy bit line DBL is not cut.

According to the present embodiment, since the fuse control circuit FSETformed in the peripheral circuit region PERI is electrically coupled tothe dummy bit line DBL used as a fuse through the dummy channel film DCHformed through the cell structure 40, the routing path whichelectrically couples the fuse control circuit FSET and the dummy bitline DBL can be shortened to a smaller length than when the routing pathis formed to bypass the cell structure 40. Thus, the distortion of aprogram voltage from the fuse control circuit FSET while transmitted tothe dummy bit line DBL through the routing path can be minimized, whichmakes it possible to prevent a program error of the dummy bit line DBL.

Referring to FIG. 8 , the second upper wiring layer 73 may include afuse which can be electrically cut. For example, the second upper wiringlayer 73 may be electrically cut for storing option information orrepair information. In FIG. 8 , CUT indicates a portion where the secondupper wiring layer 73 is cut.

The peripheral circuit region PERI may include a fuse control circuitFSET configured to program a fuse made up of the dummy bit line DBL andverify a program state. The fuse control circuit FSET may provide ahigh-level program voltage to the dummy bit line DBL.

The fuse control circuit FSET may be electrically coupled to the secondupper wiring layer 73 through the lower wiring structure LML, thevertical contact 60, the dummy channel film DCH, the dummy bit linecontact DBLC, the dummy bit line DBL and the first upper wiring contact72, and cut (or program) the second upper wiring layer 73 by applying aprogram voltage to the second upper wiring layer 73.

When a routing path between the fuse control circuit FSET and the secondupper wiring layer 73 is lengthened, the capacitance and resistance areincreased. Then, while the influence of noise increases, a signal may bedistorted during a signal transmission process, thereby causing anprogram error in which the second upper wiring layer 73 is not cut.

According to the present embodiment, since the fuse control circuit FSETformed in the peripheral circuit region PERI is electrically coupled tothe second upper wiring layer 73 used as a fuse through the dummychannel film DCH formed through the cell structure 40, the routing pathwhich electrically couples the fuse control circuit FSET and the secondupper wiring layer 73 can be shortened to a smaller length than when therouting path is formed to bypass the cell structure 40. Thus, thedistortion of a program voltage from the fuse control circuit FSET whiletransmitted to the second upper wiring layer 73 through the routing pathcan be minimized, which makes it possible to prevent a program error ofthe second upper wiring layer 73.

In the embodiments of FIGS. 1 and 8 , the semiconductor pattern 50 underthe cell structure 40 is used as a common source region, and each of thechannel films CH forms an I-shaped channel.

As illustrated in FIG. 9 , however, the semiconductor pattern 50 may beused as a pipe gate electrode, and two or more channel films CH may becoupled through a pipe line channel film PCH formed in the pipe gateelectrode. For example, a pair of channel films CH may be coupledthrough the pipe line channel film PCH, and a U-shaped channel may beprovided by the pair of channel films CH and the pipe line channel filmPCH.

FIG. 10 is a simplified block diagram schematically illustrating amemory system 600 including a semiconductor memory device 620 with athree-dimensional (3D) structure, according to an embodiment of thepresent invention.

Referring to FIG. 10 , the semiconductor memory device 620 may include asemiconductor memory, according to an embodiment of the invention asdescribed above. For example, the semiconductor memory device 620 mayinclude the nonvolatile memory (NVM) device 620. The memory system 600may also include a memory controller 610. The memory controller 610 maycontrol the semiconductor memory device 620. For example, thecombination of the nonvolatile memory device 620 and the memorycontroller 610, may be configured as a memory card or a solid state disk(SSD).

The memory controller 610 may include a static random access memory(SRAM) 611, a central processing unit (CPU) 612, a host interface (I/F)613, an error correction code (ECC) unit 614, and a memory interface615, which are electrically coupled via an internal bus. The SRAM 611may be used as the working memory of the CPU 612. The CPU 612 mayperform general control operations for data exchange of the memorycontroller 610. The host interface 613 may include the data exchangeprotocol of a host which may be coupled with the memory system 600.

The ECC unit 614 may detect and correct an error included in the dataread out from the nonvolatile memory device 620.

The memory interface 615 may interface with the nonvolatile memorydevice 620.

Although not shown, it should become apparent to a person skilled in theart that the memory system 600 may further be provided with a read onlymemory (ROM) which stores code data for interfacing with the host. Thesemiconductor memory device 620 may be provided as a multi-chip packageconstructed by a plurality of flash memory chips.

The memory system 600 may be used as a storage medium of highreliability having a low probability of an error occurring. Theaforementioned nonvolatile memory device may be provided for a memorysystem such as a solid state disk (SSD). The memory controller 610 maycommunicate with an external device (for example, the host) through oneof various interface protocols such as a universal serial bus (USB)protocol, a multimedia card (MMC) protocol, a peripheral componentinterconnection express (PCI-E) protocol, a serial advanced technologyattachment (SATA) protocol, a parallel advanced technology attachment(PATA) protocol, a small computer system interface (SCSI) protocol, anenhanced small disk interface (ESDI) protocol and an integrated deviceelectronics (IDE) protocol and the like.

FIG. 11 is a simplified block diagram schematically illustrating acomputing system 700 including a semiconductor memory device with athree-dimensional (3D) structure, according to an embodiment of thepresent invention.

Referring to FIG. 11 , the computing system 700 may include a memorysystem 710, a microprocessor (or CPU) 720, a random access memory (RAM)730, a user interface 740, and a modem 750 such as a baseband chipset,which are electrically coupled to a system bus 760. In an embodiment,the computing system 700 may be a mobile device, in which case a battery(not shown) for supplying the operating voltage of the computing system700 may be additionally provided. Although not shown in the drawing, itshould become apparent to a person skilled in the art that the computingsystem 700 may further comprise an application chipset, a complementarymetal-oxide-semiconductor (CMOS) image sensor (CIS), a mobile dynamicrandom access memory (DRAM), and so on. The memory system 710 may beconfigured, for example, as a solid state drive/disk (SSD) which uses anonvolatile memory to store data. Also as an example, the memory system710 may be provided as a fusion flash memory (for example, a NAND or aNOR flash memory).

The above-described embodiments may be realized by a device and amethod. They may be realized also by a program which performs a functioncorresponding to the configuration of each embodiment or a recordingmedium on which the program is recorded. Such realization may be easilyderived from the descriptions of the above-described embodiments by aperson skilled in the art to which the embodiments pertain.

Although various embodiments have been described for illustrativepurposes, it will be apparent to those skilled in the art that variouschanges and modifications may be made without departing from the spiritand scope of the invention as defined in the following claims.

What is claimed is:
 1. A semiconductor memory device with athree-dimensional (3D) structure, comprising: a cell region arrangedover a substrate, including a cell structure, wherein the cell structureincludes a plurality of cell gate conductive films and a plurality ofinsulation films alternately stacked over the substrate; a peripheralcircuit region arranged between the substrate and the cell region; anupper wiring structure arranged over the cell region; main channel filmsand dummy channel films formed through the cell structure, wherein thedummy channel films are suitable for electrically coupling the upperwiring structure and the peripheral circuit region, wherein the mainchannel films and the dummy channel films extend above an uppermost filmof the plurality of cell gate conductive films and the plurality ofinsulation films of the cell structure relative to the substrate,wherein the peripheral circuit region comprises: peripheral circuitelements; and a lower wiring structure suitable for electricallycoupling the peripheral circuit elements and the dummy channel films,wherein the peripheral circuit elements comprise a first peripheralcircuit element and a second peripheral circuit element suitable forreceiving a signal outputted from the first peripheral circuit element,and wherein the dummy channel films comprise: a first dummy channel filmsuitable for electrically coupling the first peripheral circuit elementand the upper wiring structure; and a second dummy channel film suitablefor electrically coupling the second peripheral circuit element and theupper wiring structure.
 2. The semiconductor memory device of claim 1,wherein the upper wiring structure comprises: a first dummy bit lineelectrically coupled to the first dummy channel film; a second dummy bitline electrically coupled to the second dummy channel film; and an upperwiring layer disposed over the first and second dummy bit lines,suitable for electrically coupling the first and second dummy bit lines.3. The semiconductor memory device of claim 2, wherein the upper wiringlayer is extended in a direction perpendicular to the bit lines and thefirst and second dummy bit lines.
 4. The semiconductor memory device ofclaim 2, wherein the upper wiring layer comprises a fuse.
 5. Asemiconductor memory device with a three-dimensional (3D) structure,comprising: a cell region arranged over a substrate, including a cellstructure, wherein the cell structure includes a plurality of cell gateconductive films and a plurality of insulation films alternately stackedover the substrate; a peripheral circuit region disposed between thesubstrate and the cell region; main channel films formed through thecell structure; first and second dummy channel films electricallycoupled to the peripheral circuit region through the cell structure; anda fuse disposed over the cell region and coupled between the first andsecond dummy channel films, wherein the main channel films and the firstand second dummy channel films extend above an uppermost film of theplurality of cell gate conductive films and the plurality of insulationfilms of the cell structure relative to the substrate.
 6. Asemiconductor memory device with a three-dimensional (3D) structure,comprising: a cell region arranged over a substrate, including a cellstructure, a peripheral circuit region disposed between the substrateand the cell region; main channel films formed through the cellstructure; first and second dummy channel films electrically coupled tothe peripheral circuit region through the cell structure; a fusedisposed over the cell region and coupled between the first and seconddummy channel films; and a fuse control circuit formed in the peripheralcircuit region which cuts the fuse and verifies the cut state of thefuse.